The present invention relates to high integration of a semiconductor device, and more particularly, to a semiconductor device manufactured in a simplified process including a self-aligned contact process and a method of manufacturing the semiconductor device.
Recently, there has been a remarkable progress in integration technology of a semiconductor integrated circuit. The high integration of a semiconductor integrated circuit is generally attained if a micro line, space, and contact pattern are realized by improving a lithographic resolution.
However, alignment technique between layers has been less improved in comparison with resolution technique in lithography. In these circumstances, if alignment allowance is ensured, an entire area size inevitably increases. This is a big problem preventing high integration of the circuit.
In an attempt to overcome the increase in area size, a method has been employed in which a contact is formed in a self-alignment manner to the gate.
For example, manufacturing steps of a semiconductor device conventionally formed by such a method are shown in FIGS. 1A to 1F.
In FIG. 1A, a device isolating region 4 is formed in the surface portion of a silicon substrate 2 and a well 2a, which has an opposite conductive type to that of the substrate 2. An n-diffusion layer 6 is formed in the surface portion of the silicon substrate 2. A p-diffusion layer 8 is formed in a surface portion of the well 2a. A gate electrode 12 is formed on the silicon substrate 2 and well 2a via a gate oxide film 10. A reference numeral 14 indicates a cap layer formed of a silicon nitride (SiN) film. Furthermore, a silicon nitride film 16 is formed on the silicon substrate 2. Note that a gate side wall 18 is formed on both sides of the gate electrode 12.
As shown in FIG. 1B, the silicon nitride film 16 is removed from the surface of the silicon substrate in each of the regions with and without the well 2a by RIE (reactive ion etching), and thereafter, impurity ions are implanted into the silicon substrate 2 and the well 2a. In this manner, N.sup.+ diffusion layers 20, 22 and a P.sup.+ diffusion layer 24 serving as a source/drain are formed. Thereafter, an interlayer film 26 is deposited over an entire surface of the silicon substrate 2.
Subsequently, as shown in FIG. 1C, a resist 28 is formed on the interlayer film 26. However, the resist 28 is not formed on a contact formation region to the source/drain of the substrate 2. Then, etching is selectively performed to the resultant structure under such a condition that the silicon nitride film 14 is not etched, as shown in FIG. 1D, using the resist 28 as a mask. As a result, a contact hole 30 is formed. Accordingly, a contact (to the gate electrode) can be formed even if an alignment allowance is not taken to the gate.
As shown in FIG. 1E, a resist 32 is deposited in the contact hole 30 and on the interlayer film 26 excluding the portion in which a contact (to the gate) is to be formed in a later step. Thereafter, a contact hole 34 is formed on the gate using the resist 32 as a mask.
Thereafter, as shown in FIG. 1F, metal wiring layers 36, 38 are formed in each of contact holes 30, 34 and on the interlayer film 26.
However, the semiconductor formation method mentioned above requires two contact hole formation steps opposite to each other, that is, the step of forming a contact hole by etching the nitride film formed on the gate (corresponding to FIG. 1E) and a step of forming a contact hole without etching the nitride film formed on the gate (corresponding to FIG. 1D). Since two steps are required for the contact hole formation, the number of processing steps increases.